The continued demand for improved digital systems for use in a variety of electronic systems and products has resulted in more stringent requirements for such digital systems. For example, modern digital systems must have increased flexibility and reliability, and are expected to require lower power supply levels and higher noise margins. The number of available terminal pins on a digital chip or device often limits the functionality of digital systems. In typical digital systems, each signal pin represents two logical values, namely a logical “0” value and logical “1” value. For increased functionality, a high-impedance state or tri-state assigned a logical value “Z” is introduced, requiring the use of tri-state decoder circuits for the detection of such “Z” value states.
Existing tri-state decoder circuits generally rely on the use of two threshold values, forcing a tri-state input signal to a mid-rail value, and comparing the tri-state input signal to the two threshold values. For example, with reference to FIG. 1, a prior art tri-state decoder circuit 100 comprises a pair of input buffers BUF2 and BUF1 and a digital conditioning circuit 102. Input buffers BUF2 and BUF1 are configured for receiving a tri-state input signal at input pin SIGNALIN, coupled between a resistor divider circuit and between a positive rail supply VDD and ground GND, and for providing an upper and lower threshold respectively, e.g., 0.7 of VDD and 0.3 of VDD. Digital conditioning circuit 102 is configured to receive output signals N2 and N1 from input buffers BUF2 and BUF1 and for providing output signals OUT2 and OUT1. With reference to FIG. 2, another example of an existing tri-state decoder circuit 200 is illustrated. Decoder circuit 200 is similar to decoder circuit 100 except having input buffers BUF2 and BUF1 being replaced with comparators COMP2 and COMP1, respectively, and further configured with a reference divider circuit comprising resistors R3, R4 and R5. The reference divider circuit is configured for generating the upper and lower threshold values, e.g., 0.7 of VDD and 0.3 of VDD.
In both decoder circuits 100 and 200, the values selected for the mid-rail value (VDD/2), and the two threshold values require high precision for correct functionality. For example, with reference to FIG. 3, a diagram illustrating detection margins for facilitating comparison and detection of a tri-state input signal at input pin SIGNALIN demonstrates that the margin for variation for the mid-rail value VDD/2 (representative of the “Z” state) is relatively small compared to the margins for the upper and lower threshold values, requiring higher precision. The precision is affected by the matching of the various components, as well as process, temperature and power supply variations. For example, resistor mismatch, comparator offset and other like impairments can make high precision difficult to obtain. Further, as the power supply is scaled down for lower power applications, the threshold values and corresponding margins further shrink, requiring even higher precision.